3 Key Takeaways from Chiplet Summit 2025

By Rachel Horton

January 24, 2025

Innovators from around the globe gathered in Santa Clara this week for the third annual Chiplet Summit to learn the latest in artifical intelligence (AI)/ machine learning (ML) acceleration, the open chiplet economy, advanced packaging methods, die-to-die interfaces, and more. The TechArena team had courtside seats for the event, and with chiplets being the underpinning technology for continued advancements of Moore’s Law, we were keen to understand the state of industry innovation.

We have been talking about an open chiplet economy on the TechArena platform since we named UCIe one of the top innovations in tech in 2022. The speed of design, efficiency of multi-process solution delivery, and opportunity for best-in-breed chiplet integration offers unquestionable opportunity for the market. But while all major compute architectures embrace chiplet designs today, the open economy of chiplet design has been slow to emerge due to missing elements, such as form factor designs, and interoperability testing still needing to be addressed by the industry. Technologists attending the event this week enjoyed opportunities to learn from industry pacesetters about the current state of addressing these gaps as discussions centered on how to create the latest chiplet designs in less time, for less cost, and in a more scalable way.

The event featured a series of keynotes from semiconductor heavyweights, including  Alphawave Semi, Arm, the Open Compute Project Foundation, Synopsys, and Teradyne. While these companies provided incredible insight to the state of the industry, there were a few takeaways that rose above the rest:

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