Chiplet integration solutions from Keysight at Chiplet Summit

By Don Dingee

January 16, 2025

Key Takeaways

• Chiplet technologies are gaining momentum, particularly in AI and 5G/6G RFIC applications, with significant presentations made by Keysight at the Chiplet Summit.
• System-level electrical layer analysis is crucial for chiplet design, particularly to ensure signal integrity, which is impacted by interconnect standards like UCIe and BoW.
• Keysight emphasizes the importance of engineering lifecycle management (ELM) for chiplet design, allowing teams to effectively manage specifications, design data, and component integration across departments.

Chiplets continue gaining momentum, fueled in large part by applications for AI and 5G/6G RFICs. Keysight has a strong presence at this year’s Chiplet Summit in Santa Clara, which includes Simon Rance in a super panel discussing “Chiplets: The Key to Solving the AI Energy Gap” and Nilesh Kamdar with a keynote on “Using Design-to-Test Workflows and Managing the IP Lifecycle in Chiplet Designs”, as well as several technical talks. Keysight previewed some of its material for the conference, focusing on three aspects of its chiplet integration solutions: system-level electrical layer analysis, a compliance testing strategy to characterize golden die and die-to-die channels, and engineering lifecycle management for chiplet design.

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