RapidChiplet: A Toolchain for Rapid Design Space Exploration of Chiplet Architectures
By Patrick Iff, Benigna Bruggmann, Maciej Besta, Luca Benini, Torsten Hoefler (ETH Zurich)
Chiplet architectures are a promising paradigm to overcome the scaling challenges of monolithic chips. Chiplets offer heterogeneity, modularity, and cost-effectiveness. The design space of chiplet architectures is huge as there are many degrees of freedom such as the number, size and placement of chiplets, the topology of the inter-chiplet interconnect and many more. Existing tools for cost and performance prediction are often too slow to explore this design space. We present RapidChiplet, a fast, open-source toolchain to predict latency and throughput of the inter-chiplet interconnect, as well as a chip's manufacturing cost and thermal stability.
To read the full article, click here
Related Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Interconnect Chiplet
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related Technical Papers
- Muchisim: A Simulation Framework for Design Exploration of Multi-Chip Manycore Systems
- Inter-Layer Scheduling Space Exploration for Multi-model Inference on Heterogeneous Chiplets
- Cambricon-LLM: A Chiplet-Based Hybrid Architecture for On-Device Inference of 70B LLM
- CATCH: a Cost Analysis Tool for Co-optimization of chiplet-based Heterogeneous systems
Latest Technical Papers
- Fast and Accurate Jitter Modeling for Statistical BER Analysis for Chiplet Interconnect and Beyond
- A3D-MoE: Acceleration of Large Language Models with Mixture of Experts via 3D Heterogeneous Integration
- ChipletPart: Scalable Cost-Aware Partitioning for 2.5D Systems
- Chiplet design basics for engineers
- Electrothermal co-optimization of 2.5D power distribution network with TTSV cooling