RapidChiplet: A Toolchain for Rapid Design Space Exploration of Chiplet Architectures
By Patrick Iff, Benigna Bruggmann, Maciej Besta, Luca Benini, Torsten Hoefler (ETH Zurich)
Chiplet architectures are a promising paradigm to overcome the scaling challenges of monolithic chips. Chiplets offer heterogeneity, modularity, and cost-effectiveness. The design space of chiplet architectures is huge as there are many degrees of freedom such as the number, size and placement of chiplets, the topology of the inter-chiplet interconnect and many more. Existing tools for cost and performance prediction are often too slow to explore this design space. We present RapidChiplet, a fast, open-source toolchain to predict latency and throughput of the inter-chiplet interconnect, as well as a chip's manufacturing cost and thermal stability.
To read the full article, click here
Related Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Interconnect Chiplet
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related Technical Papers
- Muchisim: A Simulation Framework for Design Exploration of Multi-Chip Manycore Systems
- Inter-Layer Scheduling Space Exploration for Multi-model Inference on Heterogeneous Chiplets
- Cambricon-LLM: A Chiplet-Based Hybrid Architecture for On-Device Inference of 70B LLM
- Co-Optimization of Power Delivery Network Design for 3-D Heterogeneous Integration of RRAM-Based Compute In-Memory Accelerators
Latest Technical Papers
- Corsair: An In-memory Computing Chiplet Architecture for Inference-time Compute Acceleration
- Thermal Implications of Non-Uniform Power in BSPDN-Enabled 2.5D/3D Chiplet-based Systems-in-Package using Nanosheet Technology
- Chiplets Are The New Baseline for AI Inference Chips
- Hybrid Bonding With Polymeric Interlayer Dielectric Layers Patterned by Nanoimprint Lithography
- Advanced Optical Integration Processes for Photonic-Integrated Circuit Packaging