Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges
By Peng Gu 1, Shuangchen Li 1, Dylan Stow 1, Russell Barnes 1, Liu Liu 1, Yuan Xie 1, Eren Kursshan 2
1 University of California, Santa Barbara
2 Columbia University, New York
Abstract
3D die stacking and 2.5D interposer design are promising technologies to improve integration density, performance and cost. Current approaches face serious issues in dealing with emerging security challenges such as side channel attacks, hardware trojans, secure IC manufacturing and IP piracy. By utilizing intrinsic characteristics of 2.5D and 3D technologies, we propose novel opportunities in designing secure systems. We present: (i) a 3D architecture for shielding side-channel information; (ii) split fabrication using active interposers; (iii) circuit camouflage on monolithic 3D IC, and (iv) 3D IC-based security processing-in-memory (PIM). Advantages and challenges of these designs are discussed, showing that the new designs can improve existing countermeasures against security threats and further provide new security features.
To read the full article, click here
Related Chiplet
- Interconnect Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related Technical Papers
- On hardware security and trust for chiplet-based 2.5D and 3D ICs: Challenges and Innovations
- High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions
- Challenges and Opportunities to Enable Large-Scale Computing via Heterogeneous Chiplets
- Advancing Trustworthiness in System-in-Package: A Novel Root-of-Trust Hardware Security Module for Heterogeneous Integration
Latest Technical Papers
- Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges
- MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debugging
- ATSim: A Fast and Accurate Simulation Framework for 2.5D/3D Chiplet Thermal Design Optimization
- Chiplet-Based Architectures: Redefining the Future of System-on-Chip (SoC) Design
- AuthenTree: A Scalable MPC-Based Distributed Trust Architecture for Chiplet-based Heterogeneous Systems