Hybrid Bonding With Polymeric Interlayer Dielectric Layers Patterned by Nanoimprint Lithography
By Sungwoo Jeon; Sohwi Lee and Hyunsik Yoon
Seoul National University of Science and Technology, South Korea
Recent advancements in semiconductor technology have shifted the focus of innovation toward advanced packaging technologies featuring heterogeneous integration. Among these, hybrid bonding has garnered significant attention due to its potential for achieving higher integration density and reduced interconnect lengths. To alleviate thermal stress during high-temperature processes, polymeric interlayer dielectric (ILD) offers a promising solution owing to their compliant mechanical properties and strong bonding strength. In this work, we propose a simplified patterning method for polymeric dielectric layers based on thermal nanoimprint lithography (NIL). NIL enables the patterning of ILD layers using conventional polymers such as epoxy, as it does not require photoactive materials typically used in photolithography. In this study, a thermosetting epoxy resin based on diglycidyl ether of bisphenol A (DGEBA) was employed as the dielectric material. Using NIL followed by thermo-compression bonding, we achieved hybrid bonding with a 3μ m linewidth. The bonding strength of the Cu/epoxy interfaces was measured to lie between that of conventional Cu–Cu and epoxy–epoxy bonding, reflecting the dual contributions of metal diffusion and polymer crosslinking. These results demonstrate the feasibility of nanoimprint-based dielectric patterning for fine-pitch hybrid bonding and highlight its potential for high-density packaging and 3D integration, offering a viable alternative to traditional Through-Silicon Via (TSV)-based approaches.
To read the full article, click here
Related Chiplet
- Interconnect Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related Technical Papers
- Revamping the Semiconductor Industry with Hybrid Bonding
- Thermal Issues Related to Hybrid Bonding of 3D-Stacked High Bandwidth Memory: A Comprehensive Review
- Why package lithography matters in heterogeneous chiplet integration
- Inter-Layer Scheduling Space Exploration for Multi-model Inference on Heterogeneous Chiplets
Latest Technical Papers
- MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debugging
- ATSim: A Fast and Accurate Simulation Framework for 2.5D/3D Chiplet Thermal Design Optimization
- Chiplet-Based Architectures: Redefining the Future of System-on-Chip (SoC) Design
- AuthenTree: A Scalable MPC-Based Distributed Trust Architecture for Chiplet-based Heterogeneous Systems
- THERMOS: Thermally-Aware Multi-Objective Scheduling of AI Workloads on Heterogeneous Multi-Chiplet PIM Architectures