Scaling Open Compute: RISC-V, Chiplets, and the Future of AI and Robotics

By Wei-Han Lien, Chief Architect and Senior Fellow, Tenstorrent.

As artificial intelligence and autonomous systems become increasingly pervasive, the demand for scalable, high-performance, and open computing platforms is more critical than ever. This presentation outlines Tenstorrent’s approach to advancing RISC-V beyond its embedded roots into mainstream high-performance and automotive markets through mature IP and modular architecture.We introduce Tenstorrent’s RISC-V CPU roadmap, featuring the Ascalon and Callandor cores, designed for high SPECINT performance, and the Ascalon-Auto variant, which incorporates ISO 26262-compliant safety features for ADAS and autonomous driving applications. These processors are implemented using chiplet-based design and are paired with Tensix AI accelerators, enabling efficient support for AI workloads across edge devices, data centers, and automotive platforms.Central to this platform strategy is the Open Chiplet Architecture (OCA)—a layered, open standard that facilitates interoperability across chiplets from different vendors. OCA standardizes interfaces across software, system management, transport, and physical layers, enabling modular, composable system integration and fostering a collaborative ecosystem for heterogeneous compute systems.Together, these technologies represent a unified hardware-software strategy to support ubiquitous AI computing. They position RISC-V as a competitive, open alternative to proprietary architectures, ready to power the next generation of AI-enabled and automotive systems. This presentation underscores the role of openness, scalability, and performance in shaping the future of personalized and distributed intelligence through high-performance RISC-V platforms.

Bio: 

Wei-Han Lien is a Chief Architect and Senior Fellow in Machine Learning hardware architecture. He is currently leading an architecture team in defining a high-performance RISC-V CPU, fabric, system caching, and high-performance memory subsystem for the Tenstorrent heterogeneous high-performance computation platform for AI and HPC computing. He is also leading the definition of Tenstorrent’s chiplet architecture for constructing scalable, configurable, and composable SiP with cohesive power management, security, and system management architectural definitions for compatibility.Before joining Tenstorrent, Wei-Han joined Apple through the PA Semi acquisition. He led Apple design team on the microarchitectural definitions of two of the most transformative Apple iPhone/iPad application processors from scratch, the A6 and A7 CPU projects. The Apple A7 CPU core is a solid CPU microarchitecture substrate for future generations of A-series (A7-A14) iPhone/iPad mobile processors and M-series (M1) MacBookPro processors. Before Apple, he was a distinguished architect leading P.A.Semi’s PWRficient PA6T dual O-o-O triple-issue superscalar PowerPC CPU cores. At Raza Microelectronics, he led the microarchitectures of the single-chip 40Gb scalable shared-memory switching chip and distributed-shared-memory cache coherent Ethernet switch. He joined Nexgen and AMD after graduating from the University of Michigan; he was part of a team designing the Nx586 (AMD K6), the most competitive microprocessor product to the Intel Pentium processor from 1997-1999 in the market.