Trends in 2025 Chiplet Design
Artificial intelligence and machine learning (AI/ML) applications are pushing the performance envelope to the point where chips cannot get any larger on a single die. Enter chiplets.
Dr. Jawad Nasrullah, CEO at Palo Alto Electron, takes a look at why we need chiplets, where we are now and what the biggest challenge will be for designers.
Related Chiplet
- eFPGA Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
Related Videos
- China's Chiplet Revolution: A Game Changer in Semiconductor Industry
- Enabling the Open Chiplet Economy: 3D IC Design Kits (3DK) in Action
- DAC 2025: Cadence and Its Ambition to Jumpstart the Chiplet Marketplace
- Blue Cheetah BlueLynx for Heterogeneous Integration: 16 Gbps Chiplet Interconnect IP for UCIe & BoW
Latest Videos
- Zero trust in silicon: The new security imperative for chiplet-based 3D ICs
- Beyond the data pipe: Why connectivity IP is now the system-critical layer in every 3D IC
- An Automated Interconnect Modeling Framework for Rapid Cryptolet Design Space Exploration
- DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation
- The Evolution Of UCIe