Physical AI Addressing the barriers to interoperable chiplets in automotive and robotics

David Glasco, Vice President, Engineering, Cadence Design Systems,
Bart Plackle, Senior Vice President Automotive, IMEC
Mukund Chavan, Vice President of ASIC Design, Rivian
CP Hung, VP of Corporate R&D, ASE

Chiplets enable re-use and scale in physical AI systems, but distributing functionality across independently designed dies introduces new architecture challenges.  In such systems, safety can no longer be inferred from isolated components alone; it must be established across chiplets, die-to-die interconnects (D2D), and with system-level supervision. As OCPs Open Chiplet Economy initiative launches a new workstream to define chiplet interface standards for advanced automotive and robotics applications, were assembling a panel to discuss the opportunities and challenges posed by advanced packaging and composable multi-die systems beyond the data center. Speakers from Arm, ASE, Cadence, Imec, and Rivian will discuss the priorities and role of open chiplet standards to accelerate innovation while ensuring reliability, safety, and serviceability.