Multi-Chiplet Heterogeneous Integration Packaging for Semiconductor System

By Surya Bhattacharya, A*STAR Institute of Microelectronics (IME)

Abstract:

Semiconductor system scaling has been driven by the need to pack increased functionality and performance lower power and into smaller formfactors. In past decades, system scaling was achivied primarily through CMOS chip scaling. Hyper-scale Data Centres, Generative AI, High Performance Compute, Co-packaged optics, Automotive electronics and 5G/6G/SATCOM applications have driven the industry to adopt multi-chip heterogeneous integration (MCHI) packanging to overcome chip-scaling limitatios and meet the demanding a diverse needs of Power-Perfomance- Formfactor- COST (PPFC) driven semiconductor in a single package. In this talk, we will present the challenges and opportunities that the industry encounters along the path to achieving multi-chiplet Trillion transistor packages.

Biography:

Dr. Surya Bhattacharya is Director, System-in-Package, at A*STAR Institute of Microelectronics (IME), Singapore. Over the past 30 years, he has worked on CMOS technology development, high volume product and research institute. At IME, Surya leads the packaging team to initiate and execute industry consortia projects to address challenges in advanced heterogeneous integration for system scaling. Before joining IME he served as Direcotor of Foundry Engineering at Qualcomm, working on technology bring-up and product ramps at leading foundries. Surya has a PhD in Electrical Engineering from the Unviersity of Texas at Austir and B. Tech in Electrical Engineering from the Indian Institute of Technology, Madras.