Letizia Giuliano, Qualcomm & Sophie Wang, Marvell | GSA Women's Leadership Initiative 2026

In this interview from the GSA Women's Leadership Initiative 2026, Letizia Giuliano, vice president of product management and marketing at Qualcomm Technologies, joins Sophie Wang, senior director of product engineering at Marvell Technology, to talk with theCUBE's John Furrier and Alison Kosik about why the AI system itself is becoming the new chip. Giuliano explains that as AI clusters scale, connectivity rather than compute has become the real bottleneck, likening data center design to building a racetrack capable of handling peak horsepower. She details how optical interconnects are supplementing copper as data rates push past 200 gigabits per second, creating a hybrid, heterogeneous approach throughout the data center. Wang unpacks how hyperscale manufacturing demands a "left shift" mindset, embedding reliability and test planning early into custom silicon development to manage compressed schedules and new packaging technologies.

The panel also breaks down how chiplet architectures are reshaping system design, with Giuliano detailing the delicate balance between near-zero power die-to-die interconnects and the performance needed to avoid bottlenecking AI workloads. She highlights Qualcomm's newly launched High Bandwidth Compute architecture, designed to attach compute directly to memory for improved token-per-watt efficiency. Wang walks through the economics of yield at hyperscale, noting that even a 1% yield swing can translate into millions of dollars in impact across millions of units. She also unpacks how heterogeneous integration introduces new failure modes — including delamination and microbump degradation — that demand qualification at the full package-system level rather than the individual chip. Both executives agree that solving today's networking bottlenecks will only surface new pressure points in power, thermal management and supply chain resilience. From racetrack analogies for data movement to the realities of qualifying buried interfaces inside advanced packages, Giuliano and Wang offer a grounded look at what it takes to engineer AI infrastructure at scale.