How to Simulate Chiplets 3x Faster with Xcelium
Chiplet-based designs are powerful, but testing them can be painfully slow. In this whiteboard video, we explain how Cadence’s Xcelium Distributed Simulation App helps engineers run multi-die simulations up to three times faster. Join our Industry expert from Samsung Semiconductor Research India, who breaks down the chiplet complexity into simple vocabulary and helps understand the aspects of multi-die simulations.
Related Chiplet
- Optical Chiplet
- Reverse Gearbox Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
Related Videos
- How to accelerate innovation in IC technology with chiplets and 3D ICs
- How Chiplets are Helping to Democratize Semiconductor Design with Mohit Gupta, CEO of TYLsemi
- Getting Moore with Less: How Chiplets and Open Interconnect Accelerate Cloud-Optimized AI Silicon
- Unleashing Chiplet potential with BoW - "The Knot That Ties Chiplets Together"
Latest Videos
- Agile Silicon Will Open Chiplet Architectures Keep Pace with Fast-Evolving AI Dataflows
- One Abstraction, Many Transports: Push-Mode Communication from Chiplet to Rack
- Advancing Chiplet Flexibility Updates in 2.0 OCE Transaction and Link Layer Specification
- GTC '26 - Berlin | Long-running, multi-tool Fuse Agents for 3D IC workflows
- Securing the Open Chiplet Ecosystem Defining a Common Security Architecture for FCSA