Keynote Panel: Chiplets in the RISC-V Ecosystem
Keynote Panel: Chiplets in the RISC-V Ecosystem - Aniket Saha, Tenstorrent; Dale Greenley, Ventana Micro Systems; Laurent Moll, Arteris; Rob Aitken, Synopsys; Calista Redmond, RISC-V International
Speakers: Dale Greenley, Rob Aitken, Laurent Moll, Aniket Saha
Chiplet-based architectures are being employed by a number of companies in the semiconductor industry as a solution for optimizing performance and power consumption, and addressing domain-specific computing problems.
The RISC-V community has seen this trend also, especially with companies developing high end RISC-V processors for data center, AI, automotive and HPC markets. However, chiplets have their own issues to get to production, including interconnects and communications, the processing subsystem architecture and software integration. Some companies are using current interconnect and communications technologies, while others are using photonics technologies to provide additional performance and power consumption benefits. Similarly in the processing subsystem, there are a mix of approaches including internal development of the processing components and licensing of RISC-V processor IP.
This panel represents different technology choices that have been made in the community, and will discuss those choices, all the while trying to answer the overriding question: Are chiplets the vehicle that enables high-end RISC-V based processing?
Related Chiplet
- Optical Chiplet
- Reverse Gearbox Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
Related Videos
- Keynote Panel: Chiplets in the RISC-V Ecosystem
- Paving the Road Ahead: RISC-V and Chiplet Technologies in Modern Automotive and Data Center Architectures
- EDA's Role in Chiplets - Shekhar Kapoor
- Surface codes and modular chiplets in the presence of defects
Latest Videos
- The European Chip Ecosystem
- Scaling up AI Compute, Memory and Connectivity
- CURIE: A Cycle-Accurate and Synthesizable UCIe Interface for the Agile Design and Co-Simulation of Chiplets
- Federated Chiplet Design and Simulation
- Custom HBM as a System: Co-designing the Base Die, Die to Die Power, and Package Thermals for AI Accelerators