More Data, More Redundant Interconnects
Circuits are being pushed harder and longer, particularly with AI, speeding up the aging of data paths. Photonics adds its own complications.
By Ed Sperling, Semi Engineering | May 19th, 2025
In the past, nearly all redundant data paths were contained within a planar chip using a relatively thick silicon substrate. But as chipmakers migrate from planar SoCs to multi-die assemblies, many of the data paths in a package are external. Chiplets need to communicate with other chiplets and various memories scattered throughout a package, and they need to move more data back and forth, which generates heat due to the resistance of the wires. Compounding that, the substrates need to be thinned out because that speeds up the signals, which reduces thermal conductivity.
To read the full article, click here
Related Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
- Interconnect Chiplet
Related News
- Chiplets Make Case for More Apps
- How does UCIe on chiplets enable optical interconnects in data centers?
- Imec: Breaking Connectivity Wall with Silicon Photonics and More
- Testing For Thermal Issues Becomes More Difficult
Latest News
- NIST Researchers Develop Photonic Chip Packaging That Can Withstand Extreme Environments
- Rebellions Closes $400 Million Pre-IPO and Launches RebelRack™ and RebelPOD™ to Accelerate Global Expansion
- EdgeCortix Looks To Chiplets For Third-Gen Reconfigurable AI Chip
- Agileo Automation Launches Agil'EDA to Accelerate SEMI EDA Adoption for Semiconductor Equipment OEMs
- AEM and ASE Enter Strategic Partnership to Accelerate AI and HPC Test Innovation