imec: New Methods for 2.5D and 3D Integration

By Pat Brans, EETimes Europe (October 29, 2024)

In preparation for ITF SEMICON Europa 2024 in Munich, EE Times Europe sat down with Eric Beyne, senior fellow and 3D program director at imec, to find out more about the new 2.5 and 3D integration approaches imec is preparing for industrial use.

In preparation for ITF SEMICON Europa 2024 in Munich, EE Times Europe sat down with Eric Beyne, senior fellow and 3D program director at imec, to find out more about the new 2.5D and 3D integration approaches imec is preparing for industrial use.

Research in 2.5D and 3D integration is primarily driven by the need to overcome the memory wall, where computing performance is limited by the relatively slow transfer of data between memory units and processing units. This bottleneck is driving efforts to place memory stacks closer to the chip, using different approaches that inevitably require heterogeneous integration of different dies and memory units on silicon interposers.

“We need technologies for lateral interconnect between chips, which we sometimes refer to as 2.5D,” Beyne said. “And we need 3D integration, where you use the full surface of the die to make vertical interconnects, which is more effective when your primary goal is high volume and fast I/O between the chips.”

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