Chiplets Add New Power Issues

Well-understood challenges become much more complicated when SoCs are disaggregated.

By Ann Mutschler, SemiEngineering | March 13th, 2025 

Delivering and managing power are becoming key challenges in the rollout of chiplets, adding significantly to design complexity and forcing chipmakers to weigh tradeoffs that can have a big impact on the performance, reliability, and the overall cost of semiconductors.

Power is a concern for every chip and chiplet design, even if the specifics differ based on the application. Systems vendors and leading-edge chipmakers already are using chiplets to improve performance and power efficiency, and the automotive industry is eyeing them as a way of managing different options for consumers. But while most power-related issues are well understood in a monolithic SoC, accounting for all of the possible interactions in a heterogeneous assembly of chiplets elevates those issues to a whole new level.

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