Enabling the Chiplet Era

By Pushkar Ranade

August 2, 2024

“It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected. The availability of large functions, combined with functional design and construction, should allow the manufacturer of large systems to design and construct a considerable variety of equipment both rapidly and economically.”

Gordon Moore, Cramming More Components onto Integrated Circuits, April 1965

In his prescient 1965 paper, Gordon Moore alluded to an eventual “Day of Reckoning” when he foresaw an economic imperative to break out large monolithic “functions” into smaller, interconnected “functions”. Gordon Moore was likely envisioning what eventually became Multi-Package Modules (MPMs) that are now common in everyday consumer appliances like the iPhone which combines a memory chip unit (with Dynamic Random Access Memory or DRAM) and a logic chip unit (an Application Processor Unit or APU), separately packaged and interconnected into a single larger unit. Advances in wafer-level packaging technology over the last decade have now made it possible to also envision Moore’s 1965 prediction at a single package level, where large monolithic functions (chips) can be broken into smaller functions (chiplets), connected with extremely high bandwidths to create a much larger, virtually monolithic chip within a single package.

The thriving semiconductor ecosystem that evolved over five decades to support the efficient design and manufacturing of monolithic, standalone Systems on a Chip (SoC) is evolving yet again to enable the efficient design, manufacturing and assembly of discrete chiplets into integrated Systems in a Package (SiP).  This transformation from SoC to SiP has been underway for a few years already but is now reaching an inflection point driven by a combination of technological and economic imperatives.

This paper discusses the key pre-requisites for chiplet based designs and highlights the foundational enablers that will democratize the chiplet design ecosystem and drive this transformation at-scale. 

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