Addressing the Colossal Challenge of System Co-Optimization with a Holistic Chiplet Design Methodology

By Mike Gianfagna

July 18, 2024

We all know that semiconductor systems are getting more complex, a lot more complex. The burgeoning use of AI in almost everything is certainly accelerating this trend. Faster throughput, lower latency, efficient access to massive amounts of data and the associated communication channels to tie it all together are just some of the challenges faced by chip and system designers.  If that’s not enough, the traditional innovation engine for semiconductors – Moore’s Law is slowing. New nodes are harder to get to and the improvement isn’t as large as it has been when you finally do. And extreme complexity means it all doesn’t even fit on a monolithic die anymore.  It's something of a perfect storm – a different form of the innovator’s dilemma if you will. 

There is a bright spot on the horizon that promises to restore the exponential increases we’ve all come to expect and need. Heterogeneous multi-die design is gaining traction as the way forward. As always, good and bad news here. The good news is that a multi-die approach fueled by a chiplet ecosystem, and a comprehensive design approach can keep the innovation exponential growing. The bad news is that much of the approach is new and is lacking a holistic, cohesive strategy and plan.

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