A System Architect’s Guide to Multi-Die Interconnect

By Wang-Jin Chen

July 23, 2025

The decision to create a multi-die SiP introduces a hierarchy of interconnect technologies into the system design.

One of the most critical decisions in designing multi-die systems-in-package (SiPs) is often one of the earliest: system partitioning. How many dies will there be, and how will functions be distributed among them? Will the partitioning be relatively conservative, with dies for a central SoC, perhaps an I/O controller, and memory? Or will the approach be more chiplet-oriented, with compute and control functions spread across multiple small chiplets?

When making these decisions, designers must consider many factors: they need to meet power, performance, and assembly cost goals. The availability of chiplets and the impacts of new die designs are key factors, as is compatibility with existing systems and software. Additionally, consider the availability and capability of design resources, foundries, and assembly and test facilities.

One area of discussion that touches on all these questions is interconnect technology. On-die interconnect, die-to-die connections, die-to-substrate connections, and their intra-die traces are all distinct technologies with their own mechanical requirements, power and timing implications, and supply chain implications.

The use of each type of connection in the system design will profoundly affect the completed system’s characteristics and supply chain.

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