UCIe InterOp Testchip Unleashes Growth of Open Chiplet Ecosystem

By Kalar Rajendiran, SemiWiki

December 14, 2023

Intel recently made headlines when CEO Pat Gelsinger unveiled the world’s first UCIe interoperability test chip demo at Innovation 2023. The test chip built using advanced packaging technology is codenamed Pike Creek and is used to demonstrate interoperability across chiplets designed by Intel and Synopsys. More details on this later in this writeup. This announcement marked a critical milestone in the journey toward an open and interoperable chiplet ecosystem and highlights the UCIe standard’s commitment to driving the chiplet revolution forward.

Proofpoint of UCIe InterOp

The significance of Intel’s announcement lies in its emphasis on interoperability—the ability of chiplets to communicate seamlessly and effectively, regardless of origin. The announcement marks the public debut of functioning UCIe-enabled silicon, featuring an Intel UCIe IP manufactured on Intel 3 process node and a Synopsys UCIe IP fabricated on the advanced TSMC N3E process node. These two chiplets in the Pike Creek test chip communicate via Intel’s EMIB interconnect bridge, ushering in a new era of heterogeneous chiplet technology.

The Pike Creek test chip serves as a tangible demonstration of UCIe’s capabilities, showcasing how chiplets from different vendors can work together efficiently within a single system. Intel has announced plans to transition from proprietary interface to the UCIe interface on its next-generation Arrow Lake consumer processors. This demonstrates Intel’s commitment to fostering an open, standardized ecosystem for chiplets and aligning with the industry’s shift towards UCIe.

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