Alphawave and Keysight: UCIe Compliance Validation Journey from System Simulation to Silicon By Letizia Giuliano August 13, 2024
Ready to Level-up your SOC/Chiplet Design? : Optimizing the IP-driven Approach By Prathna Sekar August 12, 2024
The UCIe 1.1 Specification: Our Journey Toward Building an Open Ecosystem of Chiplets By Brian Rea August 12, 2024
Investigating Chiplets for Scalable and Cost Effective HPC Beyond Exascale By John Shalf, Lawrence Berkeley National Laboratory August 7, 2024
Emerging Chiplet Ecosystems Enable Optimized Multi-Vendor Designs By Elad AlonBlue, Cheetah Analog July 24, 2024
3D Integration is Redefining the Semiconductor Landscape: MonolithIC 3D's Zvi Or-Bach By Zvi Or-Bach, MonolithIC 3D July 22, 2024
Multi-Chiplet Heterogeneous Integration Packaging for Semiconductor System By Surya Bhattacharya, A*STAR July 9, 2024
Intel Demonstrates First Fully Integrated Optical I/O Chiplet for More Scalable AI By Intel June 27, 2024
Introduction to UCIe Tutorial: Electrical, Form Factor, and Compliance By Zuoguo (Joe) Wu, Intel June 3, 2024
Heterogeneous 2.5/3D Chip Design Requires Integrated Tools By Kevin Rinebold, Siemens EDA June 3, 2024