Standards for Chiplet Design with 3DIC Packaging (Part 1)

 

This workshop brings together chip designers, chiplet providers, EDA tool providers, packaging and test houses and foundry partners to discuss developing common data formats, tool interfaces and process flows for a revamped supply chain.

The goal of the workshop is to identify standards that, if developed, can simplify chiplet/3DIC design from specification and tapeout to chip packaging. We envision that interoperable formats will streamline handoffs between design, verification, assembly and packaging tools. Standardized workflows will also facilitate collaboration across organizational boundaries.

Agenda (Organization - Speaker)

• OCP (ADK/MDK) - James Wong, OCP CDX Co-Lead
• Siemens & JEDEC - Michael Durkan, Director, Industry Standards
• Cadence - John Park, Director, IC Packaging
• Siemens - Tony Mastroianni, Director, Adv. Packaging, OCP CDX Co-Lead
• IBM - Arvind Kumar, Principal Research
• Palo Alto Electron - Jawad Nasrullah, CEO & Founder
• Lawrence Berkeley Lab - John Shalf, Department Head for Computer Science
• Tenstorrent - Helia Naeimi, Director, Network and Connectivity
• Nvidia - Narasimha Lanka, Prinicpal Engineer
• Enosemi - Shahab Ardalan, VP of Engineering
• OCP - James Wong, OCP CDX Co-Lead