Distributing Intelligence Inside Multi-Die Assemblies

Disaggregration requires traffic cops and in-chip monitors to function as expected over time.

By Ed Sperling, Semiconductor Engineering | June 26, 2025

The shift from SoCs to multi-die assemblies requires more and smarter controllers to be distributed throughout a package in order to ensure optimal performance, signal integrity, and no downtime.

In planar SoCs, many of these kinds of functions are often managed by a single CPU or MCU. But as logic increasingly is decomposed into chiplets, connected to each other and memories by TSVs, hybrid bonds, or standard copper wires, there are many more interactions, a greater potential for data path slowdowns caused by process variation or uneven aging, and a growing need to manage where processing happens due to different workloads, domains, and physical effects such as heat and noise.

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