Generative Design of Liquid-Cooling Channels for Thermal Management of 2.5D and 3D Integrated Advanced Packaging
By Michael Acquah, Zheng Liu
University of Michigan-Dearborn

Abstract
High power multi-chip packages require increasingly effective cooling as more heat is generated within a limited package area. This work presents a physics-guided generative design framework for liquid cooling channel topology optimization in a 2.7 kW multi-chip package containing two high power GPUs and one CPU. A conditional diffusion model generates symmetric channel layouts using maximum GPU temperature, GPU temperature spread, and pressure drop as performance targets. Generated designs are subjected to connectivity and dead-end-branch screening and are then evaluated using a calibrated reduced-order thermal-hydraulic model. Of 5,000 generated layouts, 2,220 contained a continuous inlet-to-outlet flow path and 229 satisfied the final topology-screening criteria. Multi-objective analysis identified G1016 as the thermally leading feasible design, with a predicted maximum GPU temperature of 70.30 °C, GPU temperature spread of 24.90 °C, and pressure drop of 89.72 kPa. Compared to a conventional reference topology, G1016 reduced the maximum GPU temperature, the temperature spread, and the pressure drop by 33.6%, 52.5%, and 72.8%, respectively. Independent three-dimensional conjugate heat-transfer simulation in OpenFOAM predicted a maximum GPU temperature of 66.70 °C and a pressure drop of 92.1 kPa, corresponding to ROM differences of approximately 8.6% in temperature rise and 2.6% in pressure drop. The results demonstrate that physics-guided generative design can efficiently discover non-conventional cooling channel architectures while limiting expensive full-order CFD to final validation.
To read the full article, click here
Related Chiplet
- Integrated voltage regulator (IVR) chiplet
- High-performance connectivity chiplets
- eFPGA Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
Related Technical Papers
- Wafer Warpage of Silicon Interposer in Manufacturing Processes for High Density 2.5D Advanced Packaging: Causes, Measurement, Analysis and Optimization
- On hardware security and trust for chiplet-based 2.5D and 3D ICs: Challenges and Innovations
- Intel Delivers Cutting-Edge Process Technologies to the Data Center with Intel 18A and Advanced Chiplet Packaging
- Towards efficient ESD protection strategies for advanced 3D systems-on-chip
Latest Technical Papers
- ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI
- Generative Design of Liquid-Cooling Channels for Thermal Management of 2.5D and 3D Integrated Advanced Packaging
- Thermal Tuning Overhead in Wafer-Scale Optical Interconnects for LLM MoE Training: A Cross-Layer Analysis and Ferroelectric-Based Mitigation
- An Open-Source Benchmark Suite of 3D-IC Testcases
- IC-ThermBench: An Open, Progressive Benchmark for Generalizable 2.5D/3D-IC Thermal Learning