TSMC SoIC roadmap targets 2029 chip stacking

By Brian Tristam Williams, eeNews Europe |  April 29, 2026

TSMC is pushing its 3D chip-stacking roadmap towards finer interconnect pitches and tighter integration as advanced packaging becomes a larger part of performance scaling for AI and high-performance computing designs.

The updated TSMC SoIC roadmap, reported after the company’s 2026 North America Technology Symposium in Santa Clara, points from 6 µm pitches today towards 4.5 µm by 2029. That direction matters because pitch scaling in hybrid-bonded die stacks directly affects the number of vertical interconnects that can be placed between chiplets.

TSMC separately said at its 2026 North America Technology Symposium that A14-to-A14 SoIC is set to be available for production in 2029, providing 1.8x higher die-to-die I/O density than N2-on-N2 SoIC. The company positions the technology as part of its wider 3DFabric advanced packaging family, alongside CoWoS and InFO.

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