The keeper of Moore’s Law
By Nick Flaherty, eeNews Europe (December 14, 2024)

IEDM is always eye opening for the advances of device technology. The 2024 meeting in San Francisco this week has not only shown the latest 2nm CMOS process technologies, but way beyond.
TSMC is discussing the technology for its A16 node at the end of 2026, while European researchers at imec have been showing, and making, the components for a standard cell with stacked CFET nanosheet transistors for A7 in the early 2030s.
While there used to be talk of the ‘end of Moore’s Law’ (and certainly the end of Dennard scaling) Intel has been pushing back.
“We continue to be the stewards of Moore’s Law for the industry,” said Sanjay Natarajan, SVP & GM of the Intel Technology Research Group, the newly renamed Components Research group. “We are releasing groundbreaking new technology,” he said. “We have in my opinion perhaps the strongest research development pipeline in the industry.”
He points to the combination of device technology, interconnect and packaging as vital to driving the technology forward.
To read the full article, click here
Related Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
- Interconnect Chiplet
Related News
- Is Chiplets the Answer to the End of Moore’s Law?
- Hybrid bonding: A global picture of the IP competition
- ISE Labs Investment Secures the Establishment of New Site for Semiconductor Packaging and Test in Mexico
- Ayar Labs to Showcase the Future of AI Infrastructure with Fujitsu, Intel Foundry, Corning, and Altera
Latest News
- Beyond Chiplets, CMOS 2.0 Moves Scaling into the Circuit
- TSMC and Amkor Technology Announce Long Term Partnership to Accelerate Advanced Packaging in the United States
- Ready to go just in time for the EU visit: Fraunhofer IMS Unveils New Photonics Laboratory in Duisburg
- Sony and imec unveil high-density backside connectivity module enabling next-generation 3D chip integration
- AttoTude Secures $52M in Series C Funding Round to Accelerate Interconnect Technology for Hyperscale Infrastructure