Ayar Labs Names Sankara Venkateswaran as Vice President of Engineering
Former Intel networking silicon leader joins to scale co-packaged optics for hyperscale AI infrastructure
SAN JOSE, Calif. — Feb. 23, 2026 — Ayar Labs, the leader in co-packaged optics (CPO) solutions for AI scale-up, announced the appointment of Sankara Venkateswaran as Vice President of Engineering. He joins at a pivotal stage as the company scales its solution for mass production to support hyperscale AI workloads.
“Sankara brings deep expertise in network acceleration silicon that perfectly complements our leadership in co-packaged optics,” said Mark Wade, CEO and co-founder of Ayar Labs. “His track record building world-class engineering teams makes him the ideal leader to help us advance CPO deployment and meet the massive scaling demands of AI infrastructure.”
Venkateswaran will lead Ayar Labs’ engineering organization developing the company’s TeraPHY™ optical engines, overseeing architecture, design, and product execution. With experience delivering end-to-end silicon products for networking controllers, he brings a disciplined focus on efficiency, predictability, and quality, which are critical to serving hyperscale customers who require production-grade silicon that integrates seamlessly into advanced packaging flows.
“Co-packaged optics is rapidly moving from early innovation to infrastructure necessity,” said Venkateswaran. “Ayar Labs is uniquely positioned to lead at the forefront of this transition. My focus is on delivering the most performant, compatible, and manufacturing-ready CPO solution for AI scale-up to overcome the bandwidth and power limitations of copper.
Venkateswaran has more than 26 years of experience delivering mobile, compute, networking, and infrastructure silicon products, with engineering and leadership roles at Atheros, Qualcomm, and Intel. He led multiple product programs and contributed to successful tape-outs across a range of leading-edge process nodes and foundries. At Intel, he served as Vice President of Foundational Networking Silicon Engineering, leading global teams developing Ethernet controllers and networking SoCs for hyperscale and enterprise customers under aggressive timelines.
His appointment builds on Ayar Labs’ momentum–including recent partnerships with Alchip and GUC–as the company scales its co-packaged optics solution for high-volume deployment. The company continues to lead the transition from traditional copper interconnects to a scalable CPO solution that delivers higher performance at lower power and cost.
About Ayar Labs
Ayar Labs is transforming AI infrastructure with the industry’s first co-packaged optics (CPO) solution that’s manufactured in partnership with the world’s leading semiconductor ecosystem. Ayar Labs unlocks AI performance and profitability by enabling thousands of GPUs to operate as a single unified system with the bandwidth and latency needed for hyperscale AI. Founded in 2015, Ayar Labs is funded by domestic and international venture capital firms, as well as strategic investors including AMD, Applied Ventures, Intel Capital, NVIDIA, and VentureTech Alliance. For more information, visit www.ayarlabs.com.
Related Chiplet
- Integrated voltage regulator (IVR) chiplet
- High-performance connectivity chiplets
- eFPGA Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
Related News
- Ayar Labs Closes $500M Series E, Accelerates Volume Production of Co-Packaged Optics
- Lightmatter Names Roy Kim Vice President of Product to Lead Global Deployment of Photonic Interconnects
- Ayar Labs Showcases 4 Tbps Optically-enabled Intel FPGA at Supercomputing 2023
- Ayar Labs Names Mark Wade CEO
Latest News
- proteanTecs Unveils Advanced Packaging Solutions to Improve Yield, Performance, and Reliability of Multi-Die Systems
- JCET Advances High-Aspect-Ratio TSV Technology for 2.5D and 3D Packaging
- Semiconductor Research Corporation Launches SPARC, Accelerating Industry-Driven University Research for the Next Generation of Semiconductor Innovation
- The world’s first technology 'Silicon Motherboard' Circuits are formed on both sides of the silicon substrate, reducing mounting footprint by 80%
- Avicena Ships World's First 1Tbps Evaluation Kits, Extending Its Leadership in microLED Optical Interconnects