New Tradeoffs In Leading-Edge Chip Design
By Katherine Derbyshire, Semiconductor Engineering (November 21st, 2024)
Device design begins with the anticipated workload. What is it actually supposed to do? What resources — computational units, memory, sensors — are available?
Answering these questions and developing the functional architecture are the first steps in a new design — well before committing it to silicon, said Tim Kogel, senior director of technical product management at Synopsys. Yet even these early decisions begin to constrain the physical architecture.
With a model of the proposed functionality, planners can begin to ask ‘what if’ questions. Does increasing on-chip memory improve performance enough to justify the increased cost and silicon area? What type of GPU is the best match for the anticipated workload?
To read the full article, click here
Related Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
- Interconnect Chiplet
Related News
- Advanced Chip Packaging Tools Are New Battleground in India
- Intel Unveils Chiplet Alliance To Enable New Chip Designs
- Cadence Accelerates SoC, 3D-IC and Chiplet Design for AI Data Centers, Automotive and Connectivity in Collaboration with Samsung Foundry
- Arteris Addresses Silicon Design Reuse Challenge with New Magillem Packaging Product for IP Blocks and Chiplets
Latest News
- Lam Research and CEA-Leti Expand Research and Development Collaboration to Advance Fabrication of Specialty Technologies
- Marvell Completes Acquisition of Celestial AI
- Chiplet Summit Announces Keynote Speakers
- CoAsia SEMI Commences Supply of 3D IC SoCs: Korea’s First Case, Positioning 3D IC as the Next HBM
- Eliyan Secures $50 Million in Strategic Investments from Leading Hyperscalers and AI Infrastructure Providers to Accelerate Scalable AI Systems