New Tradeoffs In Leading-Edge Chip Design
By Katherine Derbyshire, Semiconductor Engineering (November 21st, 2024)
Device design begins with the anticipated workload. What is it actually supposed to do? What resources — computational units, memory, sensors — are available?
Answering these questions and developing the functional architecture are the first steps in a new design — well before committing it to silicon, said Tim Kogel, senior director of technical product management at Synopsys. Yet even these early decisions begin to constrain the physical architecture.
With a model of the proposed functionality, planners can begin to ask ‘what if’ questions. Does increasing on-chip memory improve performance enough to justify the increased cost and silicon area? What type of GPU is the best match for the anticipated workload?
To read the full article, click here
Related Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
- Interconnect Chiplet
Related News
- Advanced Chip Packaging Tools Are New Battleground in India
- Intel Unveils Chiplet Alliance To Enable New Chip Designs
- Cadence Expands Support for 3Dblox 2.0 Standard with New System Prototyping Flows
- New AMD Patent Describes Potential Chiplet-Based GPU Design
Latest News
- The Thermal Mismatch Problem Constraining Large-Format AI Chips Has Been Solved: ACCM's Celeritas HM50 & HM001 Address Warpage, Package Bow, and Signal Loss
- PacTech Launches Scalable Modular Wet-Bench System for Advanced Semiconductor Packaging
- PulseForge Achieves Breakthrough in Ultra-Thin Wafer Processing, Demonstrating Photonic Debonding at less than 10-micron (µm) Silicon
- Credo Agrees to Acquire DustPhotonics, Accelerating Expansion into Silicon Photonics and Next Generation Optical Connectivity
- Rapidus Opens Analysis Center and Rapidus Chiplet Solutions