Chiplets Still A Challenge With UCIe 2.0
New connectivity standard brings performance improvements and a bunch of new features, but it may take years before they are adopted — and still may not result in an open chiplet market.
By Brian Bailey, Semi Engineering (January 30, 2025)
Plug-and-play chiplets are a popular goal, but does UCIe 2.0 move us any closer to that becoming a reality? The problem is that the current drivers of the standard are not after interoperability in the way that plug-and-play requires.
Released in August 2024, UCIe 2.0 touts higher bandwidth density and improved power efficiency, as well as new features supporting 3D packaging, a manageable system architecture, and more. The standard is being driven by key industry leaders, including ASE, Alibaba, AMD, Arm, Google Cloud, Intel, Meta, Microsoft, NVIDIA, Qualcomm, Samsung Electronics, and TSMC.
To read the full article, click here
Related Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
- Interconnect Chiplet
Related News
- QuickLogic and YorChip Partner to Develop Low-Power, Low-Cost UCIe FPGA Chiplets
- How do UCIe and BoW interconnects support generative AI on chiplets?
- How does UCIe on chiplets enable optical interconnects in data centers?
- UCIe Consortium Releases 2.0 Specification Supporting Manageability System Architecture and 3D Packaging
Latest News
- Avicena Launches the World’s First microLED Optical Interconnect Evaluation Kit for AI Infrastructure Innovators
- Lightmatter Achieves Record 1.6 Tbps Per Fiber to Accelerate AI Optical Interconnect
- Arm Positions Neoverse for AI and Telco Networks at MWC
- NVIDIA Compute Architecture Paves the Way for Scale-Up Optical Interconnects; CPO Penetration in AI Data Centers Expected to Rise Steadily
- CEA-Leti and NcodiN Partner to Industrialize 300 mm Silicon Photonics for Bandwidth-Hungry AI Interconnects