Chiplets Still A Challenge With UCIe 2.0
New connectivity standard brings performance improvements and a bunch of new features, but it may take years before they are adopted — and still may not result in an open chiplet market.
By Brian Bailey, Semi Engineering (January 30, 2025)
Plug-and-play chiplets are a popular goal, but does UCIe 2.0 move us any closer to that becoming a reality? The problem is that the current drivers of the standard are not after interoperability in the way that plug-and-play requires.
Released in August 2024, UCIe 2.0 touts higher bandwidth density and improved power efficiency, as well as new features supporting 3D packaging, a manageable system architecture, and more. The standard is being driven by key industry leaders, including ASE, Alibaba, AMD, Arm, Google Cloud, Intel, Meta, Microsoft, NVIDIA, Qualcomm, Samsung Electronics, and TSMC.
To read the full article, click here
Related Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
- High-performance connectivity chiplets
- eFPGA Chiplet
Related News
- How do UCIe and BoW interconnects support generative AI on chiplets?
- How does UCIe on chiplets enable optical interconnects in data centers?
- UCIe Consortium Releases 2.0 Specification Supporting Manageability System Architecture and 3D Packaging
- Why UCIe is Key to Connectivity for Next-Gen AI Chiplets
Latest News
- Applied Materials and Besi Expand Strategic Partnership to Advance Next-Generation Packaging for AI Scaling
- ficonTEC & HTSI Announce Strategic Cooperation to Scale Advanced CPO Test Solutions in Taiwan
- SignatureIP Unveils IP Library for Chiplet-based AI, HPC and Data Center Systems
- AI Drives Larger, Denser Packaging, Raising New Challenges for Equipment Makers
- Hamamatsu Photonics develops inverted emission microscope "iPHEMOS®-DDX" for failure analysis of advanced semiconductor packages