What are the challenges when testing chiplets?

By Jeff Shepard, Microcontroller Tips (March 4, 2024)

Chiplet testing begins with performance simulations during the design process. Compared with monolithic devices, heterogeneous chiplets require more complex testing, including known good die (KGD) testing, final test, and system level test. Success also depends on the implementation of design for test (DfT) based on several IEEE standards.

Chiplet designers need high-speed tools that can quickly and precisely simulate the die-to-die (D2D) interconnects, which are one of the keys to chiplet performance. For an increasing number of chiplets, simulation, and verification that the design meets the specifications of the Universal Chiplet Interconnect Express (UCIe) standard is another key consideration.

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