Chiplet Interfaces Embrace Failures

Why lane swapping is essential to meet assembly yield.

By Anne Meixner, Semi Engineering |  August 12th, 2025

Redundancy in chiplet interfaces is now a prerequisite for achieving sufficient yield in high-performance computing devices, which today are packed with tens of thousands of interconnects. And as the number and density of those interconnects increases, the prospects for yield only worsen.

For more than two decades, high-speed I/O interfaces have included reliability strategies to manage in-field system board failures. For example, the PCI Express 2.0 standard introduced in 2007 included 16 lanes for transactions. But if there was a lane failure then only 8 of those lanes were utilized, cutting the transaction rate in half. Commonly referred to as graceful degradation, this remains a strategy for computing chiplet interfaces such as UCIe.

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