Can You Build A Known-Good Multi-Die System?
Executive Outlook: Just because the various components in an advanced package work individually and separately doesn’t mean they will work post-assembly.
By Ed Sperling, Semiconductor Engineering
Semiconductor Engineering sat down to discuss the challenges of designing and testing multi-die systems, including how to ensure they will work as expected, with Bill Mullen, Ansys fellow; John Ferguson, senior director of product management at Siemens EDA; Chris Mueth, senior director of new markets and strategic initiatives at Keysight; Albert Zeng, senior engineering group director at Cadence; Anand Thiruvengadam, senior director and head of AI product management at Synopsys. What follows are excerpts of that discussion, which was held in front of a live audience at ESD Alliance 2025.
To read the full article, click here
Related Chiplet
- eFPGA Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
Related News
- Synopsys and Samsung Foundry Deepen Collaboration to Accelerate Multi-Die System Design for Advanced Samsung Processes
- How to Build a Better “Blackwell” GPU Than Nvidia Did
- UT’s Texas Institute for Electronics Awarded $840M to Build a DOD Microelectronics Manufacturing Center, Advance U.S. Semiconductor Industry
- When Can I Buy A Chiplet?
Latest News
- As AI Moves from Training to Inference, Optics Moves Closer to the Chip
- Arteris Announces Collaboration with IC-Link by imec to Accelerate Next-Gen AI and HPC Silicon
- Asahi Kasei Adds New Slitting Facility for SUNFORT™ to Meet Growing Demand for Advanced Semiconductor Packaging
- ACCM Introduces Celeritas SMC: A Production-Ready, Silicon-Matched Core for Advanced Packaging
- Socionext Addresses Datacenter Infrastructure Customer Demands for Advanced SoCs on TSMC A14 Technology