Stop Treating Fanout RDL Like Substrate Routing
Introduction
Fanout RDL routing must support tighter design margins compared to package substrate routing. Substrate routing distributes signals over larger geometries, longer paths, and many layers. Fanout RDL forces thousands of nets through a constrained interposer region at fine line-and-space, across dense bump arrays, high-speed buses, and power structures that all must coexist. Manual routing handles isolated paths, but every die placement, bump reassignment, or power-grid change triggers another round of iteration, and the process stops converging. The demo, Accelerate Multi-Die Fanout Routing with 3DIC Compiler, shows the automated path, including front-side and backside bumps, constraint-driven routing, die-to-substrate bridging, and power-plane realization, all inside the 3DIC Compiler platform.
Set the Constraints Before the Router Runs
The demo opens in the object viewer on a two-die interposer, then works through the bump structure. It turns off backside bumps to inspect the front-side flip-chip bumps and under-bump metal, then brings the backside bumps and the UBMB layer back in. In the design assistant, default rules come from the technology file, but the demo creates a non-default routing rule on RDL1 with an 18-micron routing width, assigns nets and pins, and sets minimum and maximum routing layers to RDL1 and RDL2. Signal-route options expose via-insertion patterns and routing angles for the PG nets. That constraint-first setup automates high-volume routing but preserves designer control where specialized refinement is needed.
Bridge Routing and Zero DRCs
The design must connect the two dies through a local silicon interconnect (LSI), from the die bumps to the top of the LSI, and from its backside to the interposer's UBMB layer. Die-to-package routing is set up in the task assistant with a bounding box and a routing style. The demo selects "bridge," specifies the TIV split layers, and runs automatic routing. The error browser checks then reports zero DRCs after routing. Silicon bridges combined with RDL provide localized, very high-density die-to-die links while the broader fanout region carries package-level routing, and 3DIC Compiler's auto DRC checking keeps the layout convergent rather than accumulating cleanup.
Automation With a Manual Escape Hatch
Automated routing carries the volume, but the demo also selects a via on the top layer and routes by hand using any angle, any layer, with trace widths adjusting automatically and 45-degree segments forming. Widths change on the fly, the stretch tool shifts existing routes, and new shapes, rectangles, polygons, even a circle assigned to the VDD net through the property editor, are directly created. This combination supports automation at scale, interactive routing for custom patterns, differential-pair refinement, and targeted adjustments around dense interface regions.
Power Delivery as Part of the Same Flow
Power routing must deliver current through a continuous and unbroken path spanning die, interposer, and package. The demo selects the VAA PG net in the design assistant, highlights it, and builds a flooded plane. A package metal area is defined by a rectangle boundary on RDL2 using a contour method with a sizing of 20, and applying the command realizes the plane on the net. Isolating RDL2 confirms the metal shapes, and the whole operation stays fully DRC-aware.
Watch the Demo
Fanout RDL is becoming the scalable alternative to silicon interposers for large AI and HPC packages, and its payoff comes from routing methodologies that manage dense interconnects, HBM and UCIe interfaces, die-to-package connectivity, power-grid realization, and manufacturability together, work that manual, fragmented approaches no longer keep up with. This demo shows 3DIC Compiler handling all of it in one exploration-to-signoff environment, including constraint-driven routing, bridge-based die-to-die connections, interactive refinement, and DRC-aware power planning.