Extending Moore’s Law via high-end packaging and advanced IC substrates
Yole Group organized seminar around extending Moore’s Law through high-end packaging and advanced IC substrates enabling a pathway AI generation, in France.
By 2029, high-end packaging is poised to hit $16.7 billion, fueling GenAI expansion through chiplet and heterogeneous integration. Advanced packaging market is set up to grow at a healthy pace, strongly driven by the mega-trends of HPC, generative AI, high-end laptops and workstations, and autonomous driving.
Considering all packaging platforms, 2.5D/3D interconnect is growing at the fastest rate. High-end performance packaging market is propelled by massive growth of data center AI chips, need for more computing power, bandwidth, speed, and high-end memory, and lower power consumption.
As Moore’s Law is decelerating and die cost is growing exponentially, heterogeneous integration (HI) and chiplet adoption are gaining interest to support functionality, faster time-to-market, and compensate for exponentially increasing front-end costs. 2.5D interposers and 3D stacking solutions are the key enabling packaging technologies for GenAI, GPUs, CPUs, MCUs, high-end ASICS, and accelerators.
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