Moderating Our Open Chiplet Enthusiasm. A NoC Perspective
I recently talked with Frank Schirrmeister (Solutions & Business Development, Arteris) on the state of progress to the open chiplet ideal. You know – where a multi-die system in package can be assembled with UCIe (or other) connections seamlessly connecting data flows between dies. If artificial general intelligence and industrial-scale quantum computing are right around the corner, surely any remaining issues in open chiplet design should be a snap to resolve? According to Frank, the answer is yes and no. For a couple of privileged groups, anything is possible and is being put into practice today. For larger open markets, not so much, at least not in the near term.
To read the full article, click here
Related Chiplet
- Integrated voltage regulator (IVR) chiplet
- High-performance connectivity chiplets
- eFPGA Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
Related Blogs
- Addressing the Colossal Challenge of System Co-Optimization with a Holistic Chiplet Design Methodology
- Accelerating Early-Stage explorations with Virtual Prototyping for a thriving multi-vendor chiplet ecosystem
- Accelerating an Open Chiplet Ecosystem for Automotive with Foundation Chiplet System Architecture
- OCP Open Chiplet Economy is Leading the Next Wave of AI: Inference
Latest Blogs
- Multi-Die, Multiphysics, and the New Rules of Chip Design
- Intel’s U.S. Advanced Packaging Enables Next-Generation AI Semiconductors
- Imagination & Chiplets: Scaling System Design Beyond the Monolithic SoC
- Making chiplets work for AI requires more than connectivity
- When EMC Shielding Must Bend With the Package