Moderating Our Open Chiplet Enthusiasm. A NoC Perspective
February 14, 2024
I recently talked with Frank Schirrmeister (Solutions & Business Development, Arteris) on the state of progress to the open chiplet ideal. You know – where a multi-die system in package can be assembled with UCIe (or other) connections seamlessly connecting data flows between dies. If artificial general intelligence and industrial-scale quantum computing are right around the corner, surely any remaining issues in open chiplet design should be a snap to resolve? According to Frank, the answer is yes and no. For a couple of privileged groups, anything is possible and is being put into practice today. For larger open markets, not so much, at least not in the near term.
To read the full article, click here
Related Chiplet
- Integrated voltage regulator (IVR) chiplet
- High-performance connectivity chiplets
- eFPGA Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
Related Blogs
- Addressing the Colossal Challenge of System Co-Optimization with a Holistic Chiplet Design Methodology
- Accelerating Early-Stage explorations with Virtual Prototyping for a thriving multi-vendor chiplet ecosystem
- An Open Framework for exploring Architecture Interoperability driving multi-vendor Chiplet Eco-systems
- Accelerating an Open Chiplet Ecosystem for Automotive with Foundation Chiplet System Architecture
Latest Blogs
- Stop Finding HBM Signal Integrity Problems After Routing
- Chiplet, not so fast, did you look at everything?
- AI silicon: Package becoming system architecture
- Advanced Packaging Changes the Rules for Semiconductor Health and Performance Management
- Stretching the antenna: Advanced antenna tuning with 9SW and SLATE™ advanced packaging technology on 9SW