Foundry 2.0 – the New Path Forward for Moore’s Law
NHanced Semiconductor president Robert Patti’s presentation at the recent SEMIEXPO Heartland in Indianapolis, IN described the critical role of advanced packaging in continuing the progress of Moore’s Law in semiconductor development. Following is a summary of his presentation.
In Gordon Moore’s seminal paper, he predicted a ‘Day of Reckoning’ for semiconductor scaling. That day has arrived. However, as predicted, there is another path forward for semiconductors to continue progress without relying solely on ever-shrinking devices. Advanced packaging is that new path, and it is at the heart of a new industry model known as Foundry 2.0.
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