Cadence Recognized for Accelerating AI and 3D-IC Applications by Samsung Foundry

By Cadence

February 18, 2025

Cadence and Samsung Foundry work with some of the leading semiconductor companies in the world. Together, they work to develop design solutions for next-generation AI and 3D-IC applications. Cadence and Samsung Foundry collaborate to innovate technology and methodology that enables bigger designs, addresses the requirements of more advanced process nodes, and optimizes for more performance.

Accelerating Chip Innovation for Advanced AI and 3D-IC Applications

We recently announced a broad collaboration with Samsung Foundry that includes technology advancements to accelerate design for AI and 3D-IC semiconductors, including on Samsung Foundry's most advanced gate-all-around (GAA) nodes. The ongoing collaboration between Cadence and Samsung significantly advances system and semiconductor development for the industry's most demanding applications, including AI, automotive, aerospace, hyperscale computing, and mobile. Through this close collaboration, Cadence and Samsung have demonstrated the following solutions.

Cadence.AI Enables Lower Leakage Power and Development of SF2 GAA Test Chips

Cadence, in close collaboration with Samsung Foundry, has leveraged the Cadence Cerebrus Intelligent Chip Explorer and its AI technology in both DTCO and implementation to minimize leakage power on their SF2 GAA platform. Compared to the best-performing baseline flow, the Cadence.AI result achieved a more than 10% reduction in leakage power. As part of this ongoing collaboration, a mutual customer is actively involved in the development of a test chip using Cadence.AI for an SF2 design.

Cadence Backside Implementation Flow Certified for Samsung Foundry SF2

As a result of extensive collaboration between Cadence and Samsung Foundry, a complete Cadence backside implementation flow has been certified for the SF2 node to accelerate the development of advanced designs. The full Cadence RTL-to-GDS flow, including the Genus Synthesis Solution, Innovus Implementation System, Quantus Extraction Solution, Pegasus Verification System, Voltus IC Power Integrity Solution, and Tempus Timing Signoff Solution, has been enhanced to support backside implementation requirements such as backside routing, nano TSV insertion, placement and optimization, signoff parasitic extraction, timing and IR analysis, and DRC. The Cadence backside implementation flow has been validated with a successful Samsung SF2 test chip, demonstrating the flow is ready for use.

Collaboration to Enable Solutions for Samsung Foundry's Multi-Die Offerings

The Cadence Integrity 3D-IC Platform is enabled for all of Samsung's multi-die integration offerings, and its early analysis and package awareness features are now compliant with Samsung's 3DCODE 2.0 version. In addition, Cadence and Samsung have expanded the multi-die collaboration by enabling differentiating technologies like thermal warpage analysis using the Cadence Celsius Studio Platform and system-level LVS with the Cadence Pegasus Verification System. Cadence is also supporting Samsung with a package PDK that reduces design time with the Allegro X Design Platform. Combined with the Integrity 3D-IC platform, it optimizes the package design flow.

Cadence.AI's Virtuoso Studio Flow Successfully Deployed for Analog Circuit Process Migration

Purpose-based instance mapping in the AI-powered Virtuoso Studio provided rapid retargeting of the schematics, while circuit optimization in Virtuoso Studio's Advanced Optimization Platform helped Samsung achieve a 10X improvement in turnaround time when migrating a 100MHz oscillator design from 14nm to 8nm. In addition, a FinFET-to-GAA analog design migration reference flow is available for joint customers, with successful experimental results.

Cadence mmWave RFIC Design Flow Successfully Used to Tapeout 14RF Circuit Design

Cadence and Samsung successfully taped out a 48GHz power amplifier design, representing silicon validation of the robust, full system reference flow that leverages the Cadence EMX Designer to create passive devices with fast modeling and layout automation. Full design EM extraction with the EMX Planar 3D Solver and EM-IR analysis using Voltus-XFi Technology and Quantus Extraction Solution ensured that the IC met aggressive metrics, the Pegasus Verification System was used for signoff DRC/LVS, while Visual System Simulator (VSS) software provided a seamless environment to carry out initial system-level budgeting and post-layout verification. Mutual customers can feel confident utilizing this flow to deliver leading-edge designs to market in a timely manner.

Cadence Pegasus Verification System Certified for Samsung Foundry's 4nm and 3nm Process Technologies

Through the collaboration with Samsung Foundry, the Cadence physical verification flow is optimized to allow mutual customers using Samsung Foundry's advanced nodes to reach signoff accuracy and runtime goals for a faster time to market. The Pegasus Verification System is now certified across multiple advanced nodes at Samsung Foundry, which are proven and in production by customers, with simplified, all-inclusive licensing support. The Pegasus system is integrated into the AI-powered Cadence Virtuoso Studio as iPegasus to enable in-design signoff quality DRC and interactive metal fill in the layout implementation, offering up to 4X faster turnaround times.

Cadence IP Portfolio on Advanced Samsung Nodes

The Cadence IP portfolio offers comprehensive industry solutions on advanced Samsung nodes:

• Cadence's latest IP built on Samsung SF5A includes industry-leading PHY IP for 112G-ULR SerDes, PCIe^® 6.0/5.0, UCIe^™, DDR5-8400, DDR5/4-6400 Memory, and USB 2.0, offering customers complete platform solutions.
• Cadence's PHY IP for PCIe 6.0 on Samsung SF5A has been successfully certified for PCIe 5.0 x8 compliance and demonstrated seamless interoperability with other PCIe 5.0/6.0 system and test equipment, further showcasing its PCIe solution maturity.
• Cadence is furthering its partnership with Samsung Foundry by pushing the performance envelope, designing advanced memory IP for GDDR7 on Samsung SF4X and SF2, and helping reshape the HPC/AI industry with this new memory standard.

Advanced Verification for AI Design Complexity

Samsung Foundry applied Cadence's advanced verification technologies, such as the Palladium Enterprise Emulation System, Jasper C Apps, Xcelium Logic Simulator, and system testbench generator, to tackle rising AI chip complexity and achieve time-to-market requirements in SF3.

Samsung Awards

Samsung Foundry recognized Cadence collaboration with these awards in 2024:

• Best Technical Support: Successfully qualifying Cadence tools and methodology for the SF2 process
• Best Technical Support: Successful collaboration on an advanced packaging design platform for heterogeneous integration
• Best Collaboration: Remarkable collaboration, support, and achievement on advanced LLE 2^nd phase update and silicon prediction flow
• Best Innovation: Collaboration on analog design migration and optimization

Learn more about Cadence's collaboration with Samsung.