Advancing Die-to-Die Connectivity: The Next-Generation UCIe IP Subsystem
In today’s evolving AI/ML and HPC/datacenter landscapes, die-to-die connectivity is essential for achieving high-performance and efficient data transfer. Cadence has achieved a significant milestone with the successful tapeout of its 32G UCIe standard package IP subsystem on TSMC’s 3nm (N3P) process technology. Designed to advance the performance, power efficiency, and integration of die-to-die connectivity, the subsystem features a comprehensive range of advanced capabilities, setting a new standard in ultra-fast, high-performance interconnect solutions. Building on seven years of expertise in die-to-die solutions and the success of our proprietary 16Gbps UCIe IP subsystem, this next-generation product delivers improved performance and flexibility while maintaining the reliability and precision proven by its predecessors. Like its 16G predecessor test vehicles, the entire subsystem is implemented in silicon with the ability to transfer data off-chip through high-speed I/Os. This setup enables a user to send real traffic using their SoC prototyped in FPGA and connect to our test board to develop and confirm the full software stack.
What’s New in Our Innovative 32G UCIe Solution?
-
High-speed data transfer ranging from 4Gbps to 32Gbps: This IP supports all UCIe data transfer rates from 4Gbps to 32Gbps, offering flexibility across various customer applications. This broad speed support makes the IP ideal for diverse use cases, providing scalable performance to meet the requirements of both low-power systems and high-throughput systems.
- Advanced equalization for full range of channel reach at 32Gbps: The integrated equalization functionality allows the IP to support channels up to 25mm in length at 32Gbps, ensuring reliable performance even in extended or complex physical layouts. This capability enhances the flexibility and robustness of the system’s die-to-die interconnect.
- Optimized design for 32Gbps speed and wide interoperability: The design of the IP is optimized to operate seamlessly at the UCIe standard maximum speed of 32Gbps, ensuring robust interoperability with any UCIe solution. Optimizing to 32Gbps allows the best performance metrics and wider interoperability.
- Universal interoperability for various transmitter and receiver configurations: The UCIe transmitter of Cadence’s IP supports both half-rate and quad-rate UCIe receiver implementations, ensuring broad compatibility across various receiver configurations. With the ability to generate clocks up to 16GHz, this IP provides robust support for data rates up to 32Gbps, ensuring full interoperability in diverse UCIe applications.
Related Chiplet
- Direct Chiplet Interface
- HBM3e Advanced-packaging chiplet for all workloads
- UCIe AP based 8-bit 170-Gsps Chiplet Transceiver
- UCIe based 8-bit 48-Gsps Transceiver
- UCIe based 12-bit 12-Gsps Transceiver
Related Blogs
- Advancing Die-to-Die Connectivity: The Next-Generation UCIe IP Subsystem
- Unleashing Die-to-Die Connectivity with the Alphawave Semi 3nm 24Gbps UCIe Solution
- Cadence Sets the Gold Standard for UCIe Connectivity at Chiplet Summit '24
- AI System Connectivity for UCIe and Chiplet Interfaces Demand Escalating Bandwidth Needs
Latest Blogs
- Scaling AI Data Centers: The Role of Chiplets and Connectivity
- Is a GPU, ASIC or chiplet-based SoC better for AI as we switch from training to inference?
- Siemens EDA intros next-gen ESD; focus on chiplet-design kits (CDK)
- Accelerating the AI Economy through Heterogeneous Integration
- Outlook 2025: Embracing Chiplets