System-Level Validation Across Multiple Platforms to build a Robust 2.5D Multi Foundry Chiplet Solution
By Srivatsa Rangachar Srinivasa, Dileep Kurian, Paolo Aseron, Prerna Budhkar, Vinayak Honkote, Dan Lake, Jaykant Timbadiya, Satish Yada, Suresh Kadavakollu, James Greensky, Gauthaman Murali, Anuradha Srinivasan, Ragh Kuttappa, Tanay Karnik
Intel
Abstract
The proliferation of chiplet-based designs, driven by the escalating computational demands of AI, presents unique validation challenges when integrating heterogenous chiplets. This paper investigates the complexities of realizing large-scale chiplet systems with passive silicon base scaling beyond multi-reticle approaches, particularly addressing the heterogeneity introduced by varying functionalities with diverse manufacturing origins (multiple foundries). We propose three distinct validation platforms: hardware-aware software enablement, FPGA-based prototyping for seamless hardware porting, and specialized infrastructure for silicon system measurement, to optimize system efficiency. These platforms provide a structured framework for validating and deploying complex chiplet heterogenous architectures, exemplified by our target 20-chiplet System-In-Package (SIP). We demonstrate mapping workloads onto the hashing accelerator following the proposed approach to obtain speed up between 4x – 5x compared against CPU.
To read the full article, click here
Related Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Interconnect Chiplet
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related Technical Papers
- Automakers And Industry Need Specific, Extremely Robust, Heterogeneously Integrated Chiplet Solutions
- NoCs and the transition to multi-die systems using chiplets
- A cost analysis of the chiplet as a SoC solution
- Stop-For-Top IP model to replace One-Stop-Shop by 2025... and support the creation of successful Chiplet business
Latest Technical Papers
- AuxiliarySRAM: Exploring Elastic On-Chip Memory in 2.5D Chiplet Systems Design
- System-Level Validation Across Multiple Platforms to build a Robust 2.5D Multi Foundry Chiplet Solution
- Material-Mechanistic Interplay in SiCN Wafer Bonding for 3D Integration
- Fault Modeling, Testing, and Repair for Chiplet Interconnects
- Low-Loss Integration of High-Density Polymer Waveguides with Silicon Photonics for Co-Packaged Optics