UCIe Goes Back To The Drawing Board
By Gregory Haley, SemiEngineering (February 22, 2024)
The open chiplet interconnect protocol faces some formidable challenges, but progress continues.
The integration of multiple dies within a single package increasingly is viewed as the next evolution for extending Moore’s Law, but it also presents myriad challenges — particularly in achieving a universally accepted standard integrating plug-and-play chiplets from different vendors.
To read the full article, click here
Related Chiplet
- Direct Chiplet Interface
- HBM3e Advanced-packaging chiplet for all workloads
- UCIe AP based 8-bit 170-Gsps Chiplet Transceiver
- UCIe based 8-bit 48-Gsps Transceiver
- UCIe based 12-bit 12-Gsps Transceiver
Related News
- Eliyan Supports Latest Version of UCIe Chiplet Interconnect Standard, Continues to Drive Performance and Bandwidth Capabilities to 40Gbps and Beyond to Help Meet the Needs of the Multi-die Era
- Chiplet Pioneer Eliyan Joins UCIe and JEDEC Industry Standardization Organizations, Expands Veteran Leadership Team to Accelerate Adoption of Breakthrough Die-to-Die Interconnect Solution
- QuickLogic and YorChip Partner to Develop Low-Power, Low-Cost UCIe FPGA Chiplets
- Untether AI Joins UCIe Consortium to Drive Chiplet Technology and Energy-Centric AI Acceleration
Latest News
- Baya Systems Revolutionizes AI Scale-Up and Scale-Out with NeuraScale™ Fabric
- Axelera AI Secures up to €61.6 Million Grant to Develop Scalable AI Chiplet for High-Performance Computing
- Chiplets: A Technology, Not A Market
- Enosemi and Jabil to develop advanced packaging process technology for photonic chips
- Marvell Demonstrates Industry’s Leading 2nm Silicon for Accelerated Infrastructure