UCIe Goes Back To The Drawing Board
By Gregory Haley, SemiEngineering (February 22, 2024)
The open chiplet interconnect protocol faces some formidable challenges, but progress continues.
The integration of multiple dies within a single package increasingly is viewed as the next evolution for extending Moore’s Law, but it also presents myriad challenges — particularly in achieving a universally accepted standard integrating plug-and-play chiplets from different vendors.
To read the full article, click here
Related Chiplet
- Interconnect Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related News
- Eliyan Supports Latest Version of UCIe Chiplet Interconnect Standard, Continues to Drive Performance and Bandwidth Capabilities to 40Gbps and Beyond to Help Meet the Needs of the Multi-die Era
- Chiplet Pioneer Eliyan Joins UCIe and JEDEC Industry Standardization Organizations, Expands Veteran Leadership Team to Accelerate Adoption of Breakthrough Die-to-Die Interconnect Solution
- QuickLogic and YorChip Partner to Develop Low-Power, Low-Cost UCIe FPGA Chiplets
- Untether AI Joins UCIe Consortium to Drive Chiplet Technology and Energy-Centric AI Acceleration
Latest News
- Intel’s Expanding IP Portfolio in Co-Packaged Optics
- Rebellions Scales Global Growth with Silicon Valley backed Series C
- Rebellions Accelerates Global Expansion and Strengthens Customer-centric Strategy with Significant Executive Appointments
- Tower Semiconductor Announces New CPO Foundry Technology Available On Tower’s Leading Sipho and EIC Optical Platforms
- How Advanced Packaging is Unleashing Possibilities for Edge AI