Synopsys 3DIO Solution for Multi-Die Integration (2.5D/3D)

By Lakshmi Jain, Principal Product Marketing Manager & Wei-Yu Ma, Principal Technical Product Manager, IO Libraries, Synopsys

Accelerate Scaling of System Functionality

The demand for high performance computing, next-gen servers, and AI accelerators is growing rapidly, increasing the need for faster data processing with expanding workloads. This rising complexity creates two major challenges: manufacturability and cost. From a manufacturing perspective, these processing engines are approaching the maximum size of the reticle that the lithography machine can etch; and with a very large die size and correspondingly decreasing yield, the cost per die can increase significantly.

Gordon Moore once said, “It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected.” In chip design, to address the demands of increased performance, the industry is moving from system-on-chip (SoC) to system-in-package (SiP) by using wafer-level packaging.

A heterogeneous SoC entails partitioning the SoC at the IO or core level, using a modular approach with different building blocks. This offers several advantages, including supporting SoCs that are growing beyond reticle size, improving die yield, and enabling design modularity. However, a heterogeneous die introduces new challenges which include increased design complexity due to close interaction between the dies and package, supporting testability across assembly and manufacturing processes, and thermal management due to the proximity of the dies. 3D integration enables heterogeneous integration of IC chips fabricated with different technologies and materials, and thus permits the realization of integrated, sophisticated, and multifunctional microsystems that have high performance, low cost, and compact size requirements.

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