Automated Driving: ZF and SiliconAuto Reveal New I/O Interface Chip with Companion Microcontroller

• First live and real-time demonstration of an I/O specialized chip that performs ADAS/AD data acquisition and pre-processing in real time
• ZF’s I/O interface chip is tightly coupled with SiliconAuto’s XMotiv™ M3 microcontroller
• System is fully agnostic to the choice of high-performance SoC, enabling OEMs to integrate any preferred solution via standardized high-speed interfaces

Friedrichshafen, Nuremberg -- March 16, 2026 -- At the Embedded World 2026 electronics exhibition, ZF and SiliconAuto jointly showcase a new I/O interface chip and microcontroller design for automotive high-performance computers. It is the world’s first live demonstration of real-time sensor data acquisition and pre-processing on silicon to enable the next generation of autonomous driving.

The demonstration is based on a new ZF I/O interface chip design with the SiliconAuto’s XMotiv™ M3 microcontroller used as a safety controller. The new chip architecture represents a groundbreaking alternative to current monolithic System-on-Chip (SoC) from established providers, offering a scalable, cost efficient, and high-performance pathway for the next generation of autonomous driving systems. The Embedded World 2026 takes place in Nuremberg, Germany, from March 10 to 12.

ZF collaborated with SiliconAuto to demonstrate an automotive high-performance compute solution for Advanced Driver Assist Systems (ADAS) and Automated Driving (AD). The solution is based on a new I/O interface chip that integrates all required automotive sensor‑interface intellectual property (IP), along with sensor pre‑processing capabilities such as low‑latency camera Image Signal Processing (ISP) and on‑chip radar signal processing. The Interface Chip is tightly coupled with SiliconAuto’s XMotiv™ M3 microcontroller and is agnostic to the OEM’s preferred performance SoC, enabled by standardized high‑speed parallel interfaces like PCIe or Ethernet.

The solution offers clear scalability for automotive high-performance computers from the entry segment up to premium vehicles. It also reduces power consumption by limiting data transfers to Double Data Rate (DDR) memory and by reducing clock speeds. The I/O interface chip provides the flexibility to connect to any generation of the latest low‑power AI inference engines.

The chip is manufactured in a lower-cost processing node and offloads sensor data acquisition tasks and sensor data pre-processing to free-up expensive central processing unit (CPU) power on the performance SoC. As such, the expensive application cores of the performance of SoC can fully concentrate on perception and driving functions.

The solution is designed with the potential for future upgradeability to new vehicle generations, enabling one or several chips/chiplets to be updated, possibly without the need for a complete redesign.

Powerful Integration with SiliconAuto’s XMotiv™ M3 Controller

ZF’s I/O interface chip is tightly coupled with SiliconAuto’s XMotiv™ M3 microcontroller, which functions as the safety controller, responsible for fast and secure boot, housekeeping, power sequencing, clock control, reset supervision, enabled by its 160 MHz core speed peripherals.

A flexible, scalable alternative to traditional high-performance computing SoCs

Unlike traditional solutions, the ZF/SiliconAuto design is:

Agnostic to any performance SoC, enabling OEMs to select their preferred compute platforms via standardized high-speed interfaces such as Ethernet, PCIe or UCIe, even if the performance SoC lacks dedicated automotive sensor interfaces like CSI-2, LVDS, CAN, ETH, or LIN.

• Modular and upgradable, allowing OEMs to update only the required chiplets rather than redesigning entire HPC architectures.
• Designed for deterministic data streaming, enabling precise time stamping and synchronization across all connected sensors.
• Highly energy efficient, thanks to optimized DRAM/SRAM structures and reduced data transfer loads to DDR memory.

This combination positions the new chip as a strong alternative to current market leaders by reducing CPU load, improving overall system efficiency, and providing a scalable path from entry‑level ADAS systems up to SAE Level 4 automated driving.

Towards an Open, Chiplet Based Automotive Compute Future

The future evolution of the platform will focus on integrating open standards-based die-to-die interconnects such as UCIe, transforming the I/O chip into a fully compliant I/O chiplet. This will allow OEMs to independently select, integrate, and upgrade compute, AI inference, and I/O components, ensuring long term design flexibility and data sovereignty.

Sustainability and European Technological Sovereignty

The project was supported by the German Federal Ministry for Education, Research and Space (BMFTR) under the ZuSEKI-mobil program under grant 16ME0895, aiming to foster trustworthy, secure, and sustainable microelectronics within Europe. The modular chiplet based approach extends HPC lifetime, reduces energy consumption, and supports climate-friendly mobility technologies.