Chip Architectures Becoming Much More Complex With Chiplets
Options for how to build systems increase, but so do integration issues.
By Ed Sperling and Ann Mutschler, Semi Engineering (January 30th, 2025)
The migration from monolithic SoCs to chiplet-based designs is creating a confusing array of options and tradeoffs for design teams working at the leading edge, and the number of choices is only going to increase as third-party chiplets begin pouring into the market.
That hasn’t dampened the appetite for chiplets, however, which are deemed essential for future generations of semiconductors for several reasons.
To read the full article, click here
Related Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
- Interconnect Chiplet
Related News
- Alphawave Semi Highlights Why the Next Generation of AI Advances Demand Chiplet Architectures at EE Times: The Future of Chiplets
- Strategic alignment between imec and Japan’s ASRA aims to harmonize standardization of automotive chiplet architectures
- Ayar Labs Unveils World's First UCIe Optical Chiplet for AI Scale-Up Architectures
- Intel Unveils Chiplet Alliance To Enable New Chip Designs
Latest News
- GUC Announces Tape-out of UCIe 64G IP on TSMC N3P Technology
- GLS and APES Announce Advanced Semiconductor Packaging Partnership
- Ayar Labs Names Sankara Venkateswaran as Vice President of Engineering
- Baya Systems and Aion Silicon Partner to Accelerate Next-Generation SoC and Chiplet Designs
- ADTechnology and Fraunhofer IIS Join Forces for Advanced ASIC and Chiplet Development