Zero ASIC Releases Logik, an RTL-to-bitstream flow for FPGAs

April 3, 2024 -- Zero ASIC proudly announces Logik, a lightweight FPGA RTL-to-bitstream flow powered by Zero ASIC's Silicon Compiler solution for circuit design automation flow control. Logik enables users to generate bitstreams for FPGAs with a Python-driven, single execution step by sequencing the execution of multiple open source tools in an FPGA CAD tool chain.

In addition to Silicon Compiler, Logik builds on top of other well established open-source projects used in FPGA design flows, including

• Yosys -- Logic synthesis tool
• VPR -- FPGA place and route tool
• GHDL -- VHDL parser
• Surelog -- SystemVerilog parser

The beauty of Logik is its simplicity. Users need only write a short Python script to aggregate design data and execute the flow. Logik executes FPGA synthesis, placement, routing, and bitstream generation in sequence. Silicon Compiler's metrics reporting features are used to report key results when the job is done.

The Logik flow is currently offered with built-in support for a single eFPGA device called logik_demo. The logik_demo eFPGA offers 6576 4-input LUT/flip-flop pairs, 16 multiply-add engines (MAEs), and 16 block RAMs as its logic resources. For I/O interfaces, logik_demo offers 64 general-purpose I/O and three universal memory interfaces (UMI). In addition to using the logik_demo architecture to evaluate the RTL-to-bitstream flow, users may simulate generated bitstreams in the cloud with Zero ASIC's digital twin platform.

Developers can extend Logik's support to the FPGA architecture of their choice. The requirements for doing so consist of developing a VPR-compatible model of the FPGA, architecture metadata files to support bitstream generation, and a lightweight Python driver to integrate the FPGA into Logik.

For information on how to install and use Logik, please visit the Logik Github repository.