Reducing the barrier to ASICs with chiplets
To unlock the true power of chiplets, several hard problems need to be solved
By Designing Electronics North America
For the last 50 years, the semiconductor industry has been all about monolithic integration, doubling the number of transistors on a single chip every two years. The results have been nothing short of miraculous, with electronics getting both cheaper and better year over year.
However, as we approach the physical (atomic) limits of device scaling, we now need to find new ways of improving the energy and cost efficiency of electronics. While physical scaling may be saturating, fortunately there remains plenty of room at the bottom in terms of cost, energy, and time. Hyper- specialized circuits have demonstrated 100 to 1000x Size-Weight-Area-Power-Cost (SWAP-C) advantages over general purpose processors. Similarly, specialized devices and materials can offer 10 to 100x SWAP-C advantages over CMOS logic processes.
These two promising pathways are currently blocked by two fundamental economic challenges:
- Designing complex specialized circuits in the form of application- specific integrated circuits (ASICs) can cost over $100M and take years to complete.
- Integrating new specialized materials and devices into advanced CMOS processes is economically impractical.
An elegant solution to both of these challenges is the introduction of “chiplets,” which are tiny integrated circuits (ICs) with partial functionality designed to be combined with other chiplets within a single package to create a complete chip, which is also known as a multi-die system.
If implemented correctly, chiplet technology promises to enable custom silicon development with the design cost of PCBs and the SWAP-C of ASICs.Unfortunately, the benefits of chiplet technology have to date been accessible to only a small number of giant semiconductor vendors who leverage chiplets to improve production yields and to reduce NRE costs for multi-SKU product families.
To unlock the true power of chiplets, several hard problems need to be solved as follows
To read the full article, click here
Related Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
- Interconnect Chiplet
Related News
- DreamBig Semiconductor Announces Partnership with Samsung Foundry to Launch Chiplets for World Leading MARS Chiplet Platform on 4nm FinFET Process Technology Featuring 3D HBM Integration to Solve Scale-up and Scale-out Limitations of AI for the Masses
- Breaking the Memory Wall: How d-Matrix Is Redefining AI Inference with Chiplets
- NcodiN Secures €16M Seed Round to Break AI’s Main Bottleneck with the World’s Smallest Laser
- Vertical Compute raises €57M to solve the AI memory bottleneck with new high density memory
Latest News
- Quantum Computing Inc. Completes Acquisition of NHanced Semiconductors, Inc.
- GlobalFoundries qualifies SLATE™ advanced packaging technology on 9SW platform for next-generation radio frequency applications
- Qnity Powers the Transition from Shrink to Stack with Advanced Packaging Solutions
- NHanced Semiconductors President Robert Patti to Deliver Plenary Presentation on the Critical Role of Advanced Packaging at the 2026 Lithography Workshop
- Intel Announces Leadership Appointment at Intel Foundry to Accelerate Development and Manufacturing