Five workflows for tackling heterogeneous integration of chiplets for 2.5D/3D

By Kevin Rinebold, Siemens EDA and Todd Burkholder, Siemens DISW
New Electronics | May 26, 2025

Keeping pace with Moore’s law continues to be challenging and is driving adoption of innovative packaging technologies that support continued system scaling while doing so at lower costs than comparable monolithic devices.

These packaging technologies disaggregate what would typically be a homogenous, monolithic device, like an ASIC or SoC, into discrete, unpackaged dies, known as chiplets, specifically designed and optimised for operation within a package in conjunction with other chiplets. This is also referred to as heterogenous integration (HI), where multiple dies or chiplets are integrated into a system-in-package (SiP) design.

Heterogeneously integrated SiP devices offer considerable benefits, including higher performance, lower power usage, smaller area, lower cost, and faster time to market. However, thus far they are designed and produced by only a small number of advanced users. Broad industry proliferation will require standardisation of chiplet models and die-to-die connectivity IP - efforts currently underway - supported by new workflows.

To read the full article, click here