First Forays Into True 3D-IC Designs
Risk is high for pioneers of chiplet stacking, but the rewards could be significant. This will get easier, though.
By Ed Sperling, Semi Engineering | September 25th, 2025
Semiconductor Engineering sat down to discuss initial forays into 3D-ICs and what problems early adopters will encounter, with John Ferguson, senior director of product management at Siemens EDA; Mick Posner, senior product group director for chiplet at IP solutions in Cadence‘s Compute Solutions Group; Mo Faisal of Movellus; Chris Mueth, new opportunities business manager at Keysight Technologies, and Amlendu Shekhar Choubey, senior director of product management for Synopsys‘ 3D-IC compiler platform.
To read the full article, click here
Related Chiplet
- Integrated voltage regulator (IVR) chiplet
- High-performance connectivity chiplets
- eFPGA Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
Related News
- Ansys Enables 3D Multiphysics Visualization of Next-Generation 3D-IC Designs with NVIDIA Omniverse
- Ansys Thermal and Multiphysics Solutions Certified for Intel 18A Process and 3D-IC Designs
- SEMIFIVE Strengthens AI ASIC Market Position Through IPO “Targeting Global Markets with Advanced-nodes, Large-Die Designs, and 3D-IC Technologies”
- Keysight Unveils 3D Interconnect Designer for Chiplet and 3DIC Advanced Package Designs
Latest News
- Point2 Completes $136M Series B Funding with Arm, LB Investment, and Maverick Silicon
- Multibeam Appoints Interim CFO Following $200M Funding Milestone
- Multibeam Signs $140 Million Letter of Intent with the U.S. Department of Commerce
- Credo to Contribute OmniConnect Scale-In Interconnect Solution to the Open Compute Project to Address AI Inference Memory Wall
- Silicon Box Ships 500M Units at High Yield, Expands Production Capacity for Panel-Level Packaging