Ayar CEO: ‘Copper Is Already Broken; Agentic AI Will Require Optical I/O’
By Sally Ward-Foxton, EETimes (October 7, 2024)

SAN JOSE, California—At the AI Hardware Summit, Ayar Labs CEO Mark Wade presented the results of a sophisticated simulation of large-scale inference systems built by the company to assess what will be required to make next-generation versions of generative AI models economical.
The results show that optical die-to-die interconnects, like Ayar’s technology, will be required to scale LLM inference for next-gen models in a way that makes economic sense. The simulator also provides a useful way to assess the current state of so-called “tokenomics” (the economics of providing and building products on LLM inference APIs).
To read the full article, click here
Related Chiplet
- High-Density Electronic-Photonic Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
Related News
- Ayar Labs CEO: Optical Chiplets Coming to SOCs Soon
- Ayar Labs Names Mark Wade CEO
- Ayar Labs to Showcase Optical Interconnect Solutions to Redefine AI Infrastructure at OFC 2024
- Intel Demonstrates First Fully Integrated Optical I/O Chiplet
Latest News
- Xanadu and Tower Semiconductor Deepen Strategic Collaboration to Accelerate Photonic Quantum Hardware Innovation
- EV Group Unveils Next-Generation EVG®120 Resist Processing System for High-Volume Manufacturing
- CEA Demonstrates First Dynamically Routed Electro-Optical Router for Photonic Interposers
- Renesas Develops SoC Technologies for Automotive Multi-Domain ECUs Essential for the SDV Era
- Keysight Unveils 3D Interconnect Designer for Chiplet and 3DIC Advanced Package Designs