2.5D/3D chip technology to advance semiconductor packaging

A team of researchers from the Institute of Science Tokyo (Science Tokyo), Japan, has conceptualised an innovative 2.5D/3D chip integration approach called BBCube.

By Jean-Pierre Joosting, eeNews Europe | June 23, 2025

Traditional system-in-package (SiP) approaches, where semiconductor chips are arranged in a two-dimensional plane (2D) using solder bumps, have size-related limitations, warranting the development of novel chip integration technologies. For high-performance computing, the researchers developed a novel power supply technology by employing a 3D stacked computing architecture, which consists of processing units placed directly above stacks of dynamic random-access memory, marking a significant advance in 3D chip packaging.

To implement BBCube, the researchers developed key technologies involving precise and high-speed bonding techniques and adhesive technology. These new technologies can help address the demands of high-performance computing applications, which require both high memory bandwidth and low power consumption, with reduced power supply noise.

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