GUC Leverages 3DIC Compiler to Enable 2.5D/3D Multi-Die Package
In the rapidly evolving world of ASIC design, the shift from monolithic to 2.5D and 3D multi-die architectures represents a significant leap forward. This approach, which integrates multiple chiplets (also knowns as dies) into a single package, demands not only a new level of IC design innovation but also an increased complexity in coordination and integration. At the forefront of this technological revolution is Global Unichip Corp. (GUC), which has effectively harnessed the power of Synopsys’ 3DIC Compiler, a unified exploration-to-signoff platform, to streamline its chip design processes and reduce overall cycle time.
GUC recently presented their multi-die tape-outs at SNUG Silicon Valley 2024, which were made more efficient by Synopsys’ 3DIC Compiler through the implementation of die floorplanning and related bump assignments. Further checks to physical and logical connectivity, and quick sync-ups of the information from die to die, shortened chip design cycle timelines for GUC’s 2.5 and 3D CoWoS designs.
2.5D and 3D IC Design Challenges
This distinction between 2.5D and 3D IC design approaches becomes critical in addressing the increasing demand for higher performance and more integrated systems. Each method comes with its unique set of challenges and benefits, tailored to specific application needs.
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