Industry Leaders Discuss “Overcoming the Challenges of Multi-die Systems Verification”
Lauro Rizzatti, hardware-assisted verification consultant, served as moderator for a well-attended and lively 2024 DVCon U.S. panel discussion on the challenges in multi-die systems verification.
The hour-long session featured panelists Alex Starr, AMD Corporate Fellow; Bharat Vinta, Director of HW Engineering at Nvidia; Divyang Agrawal, Sr. Director of RISC-V Cores at Tenstorrent; and Arturo Salz, Synopsys Fellow.
What follows is a shortened panel transcript, edited for readability.
Lauro
How is multi-die evolving and growing? More specifically, what advantages have you experienced? Any drawback you can share?
To read the full article, click here
Related Chiplet
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- Ncore Multi-Die Interconnect IP
- Integrated voltage regulator (IVR) chiplet
- High-performance connectivity chiplets
- eFPGA Chiplet
Related Blogs
- Streamlining Functional Verification for Multi-Die and Chiplet Designs
- Why 2023 Holds Big Promise for Multi-Die Systems
- Synopsys and Alchip Accelerate IO & Memory Chiplet Design for Multi-Die Systems
- TSMC Advanced Packaging Overcomes the Complexities of Multi-Die Design
Latest Blogs
- Chiplet Modularity Is Becoming Part of the AI Architecture
- Hierarchies Of Interconnects Are As Important As Compute And Memory
- UALink over UCIe 3.0: Maximizing Performance for Chiplet-based Designs
- Physical AI Doesn't Just Scale Up. It Scales Out.
- Ayar Labs and GUC Complete Successful Thermal Co-Simulation Testing of Co-Packaged Optics