Industry Leaders Discuss “Overcoming the Challenges of Multi-die Systems Verification”
Lauro Rizzatti, hardware-assisted verification consultant, served as moderator for a well-attended and lively 2024 DVCon U.S. panel discussion on the challenges in multi-die systems verification.
The hour-long session featured panelists Alex Starr, AMD Corporate Fellow; Bharat Vinta, Director of HW Engineering at Nvidia; Divyang Agrawal, Sr. Director of RISC-V Cores at Tenstorrent; and Arturo Salz, Synopsys Fellow.
What follows is a shortened panel transcript, edited for readability.
Lauro
How is multi-die evolving and growing? More specifically, what advantages have you experienced? Any drawback you can share?
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