Industry Leaders Discuss “Overcoming the Challenges of Multi-die Systems Verification”
March 18, 2024
Lauro Rizzatti, hardware-assisted verification consultant, served as moderator for a well-attended and lively 2024 DVCon U.S. panel discussion on the challenges in multi-die systems verification.
The hour-long session featured panelists Alex Starr, AMD Corporate Fellow; Bharat Vinta, Director of HW Engineering at Nvidia; Divyang Agrawal, Sr. Director of RISC-V Cores at Tenstorrent; and Arturo Salz, Synopsys Fellow.
What follows is a shortened panel transcript, edited for readability.
Lauro
How is multi-die evolving and growing? More specifically, what advantages have you experienced? Any drawback you can share?
To read the full article, click here
Related Chiplet
- DPIQ Tx PICs
- IMDD Tx PICs
- Near-Packaged Optics (NPO) Chiplet Solution
- High Performance Droplet
- Interconnect Chiplet
Related Blogs
- Streamlining Functional Verification for Multi-Die and Chiplet Designs
- Why 2023 Holds Big Promise for Multi-Die Systems
- Synopsys and Alchip Accelerate IO & Memory Chiplet Design for Multi-Die Systems
- TSMC Advanced Packaging Overcomes the Complexities of Multi-Die Design
Latest Blogs
- Accelerating Chiplet Innovation with a New Partner Ecosystem
- Accelerating Multi-Die Innovation: How Synopsys and Samsung are Shaping Chip Design
- Six critical trends reshaping 3D IC design in 2026 and beyond
- AI Energy Gap and Chiplets: Why Data Movement Matters
- The Economies of Disaggregation: Why the Future is a System-of-Chiplets